Design and Realization of TFT LCD Driver Circuit based EPM240.doc

1、1Design and Realization of TFT LCD Driver Circuit based EPM240Abstract： This paper introduces the implement method of the controller of a CPLD TFT based on the LCD digital display， using CPLD to achieve TFT-LCD display timing generation， display image processing， double memory read-write rotation co

2、ntrol functions. This design according to the actual demand， cut on the interface function of special display control chip， custom display control function， enhance the system reliability and design flexibility. Applied to a liquid crystal display control unit， solve practical problems in engineerin

3、g. Keywords： EPM240； TFT Driver； design program 0 Introductions The flat panel display technology with TFT as the core of the display market has occupied an increasingly large share， the electrical properties of TFT superior to the display screen can be high speed， high brightness， high contrast dis

4、play of information， and it has been widely used in various OLED， LCD display device. In recent years， in order to show the effect of the further improvement of TFT -LCD， T FT -OLED， the 2industry of the drive and control method of a variety of different materials screen characteristics， such as liq

5、uid crystal field sequential display 1， OLED time ratio gray-scale display 2， at present， the study of the control circuit of periphery widely attention. The paper takes the TFT_LCD display with 480*272 digital input as an example， introduces a method to implement TFT-LCD interface based on STM32 pr

6、ocessor. The normally need to use the LCD control chip to solve the LCD problem. 1 The structure of system System frame as shown in figure 1. The system is composed of CPLD， RAM， RAM display program execution and TFT-LCD. CPLD （dotted around） chosen is the ALTER EPM240， RAM IDT uses IS61LV51216AL， L

7、CD color TFT-LCD screen 480*272. In the internal CPLD is composed of a timing switch， address， data separation， toning circuit and embedded CPU is composed of five parts. Circuit schematic diagram shown in figure 2. This paper uses CPLD Alteras EPM240， it is one of series of MAX ? II devices. MAX ?

8、II device series is a non-volatile type， the use of programmable logic， it uses the new CPLD architecture of a breakthrough. Half of the original MAX device is that the new architecture of the cost， power consumption is 31/3， its density is 4 times， but its performance is two times. MAX II CPLD is t

9、he cost of all CPLD series products in the lowest， the highest power density and minimum device. 0.18 M6 layer metal Flash technology based on cost optimization， MAX II device series has the advantages of all the CPLD， for example， non-volatile， availability， ease of use and fast transmission delay.

10、 Using the TQFP package EPM240 has 100 pins， wherein the I/O port 80， for use by the user. Inside there are 240 macrocells for use by the user， provide the user program memory space is 8K. So rich in resources， can meet a variety of needs. IS61LV51216AL is a memory page storage mode of RAM， the stor

11、age capacity is 1M*16. Manufactured using CMOS technics， pin number is 50， the TSOP package. Power supply voltage of 3.3V， low power consumption， read and write operation is simple， can block the operation， improve the speed and performance of the overall. A read and write operations may need dozens

12、 of nanoseconds， very fast， and can meet the need of LCD screen display. 2 The design of main circuit 2.1 The design of timing generating circuit The timing generating circuit is a main part of the design. First， we convert the system clock input frequency by CPLD 4witch have two PLL circuit modules

13、， this paper， one of PLL generates a clock of 100MHz. We re-design a 12-bit counter （the line counter） witch counts 3200 pulses Of display， line synchronizing clock generating TFT_LCD This counter also generates TFT_LCD signal （DE）. The counter output or TFT_LCD the Reading show the lower 8 bits of

14、the address of the cache RAM （RAM in 32-bit data width）. Another design a 9-bit counter （ field counter） ， with the count of its line sync signal can be generated TFT_LCD field synchronization signal， the output of this counter can be used as TFT_LCD read RAM address high 9. External asynchronous WR

15、 write data： 2.2 Toning circuit The actual palette circuit chip take advantage of CPLD internal RAM， the data generated by the Quartus software 24 256 bytes of RAM or ROM， RAM， or ROM address lines connected to LCD data latches the output of the selection circuit， data the selection circuit is the 3

16、2-bit data， to select the corresponding 8-bit data at the time determined by the T0-T3. When T0 when the election D 24-D 31， when the election when T1 D 0-D 7 D 8-D 15 election， when T2 when T3 in D 15 -D 23. The reason why the data is designed to time T0 5selected D 24-D 31， because TFT_LCD read ca

17、che RAM， T0 end of the cycle to the new data is latched into the “LCD-read DATA” end， new data only in the T1 cycle can begin to show. The toner the output of the circuit is a 3 * 8 = the 24bit as used herein TFT_LCD is 3 * 6bit so only with the corresponding 8bit low 6bit. Toning circuit design cho

18、ices RAM type can be rewritten by the CPU the a toning circuit of RAM， richer color display. 2.3 The design of address switching and data separation circuit Figure 4 is an address switching circuit， all of the circuitry can launch the 17-bit address by one bit for example. In Figure 4， RAM_ADD = （LC

19、D_ADD LCD_ strobe） + （CPU_ADD CPU_RAM_ strobe） ） and the “LCD_ read strobe“ signal “CPU_RAM_ strobe“ signal at any point in time can only have at most one is valid， so when the “LCD_ read strobe effect“ signal “CPU_RAM_ strobe“ the RAM_ADD switch to the appropriate address online. Such as when a the

20、 moment “LCD_ read strobe“ signal “CPU_RAM_ strobe“ wholly invalid RAM_ADD output should be all “0“. Figure 4 is a data separation circuit， similarly， in Figure 4 this one may be the introduction of the 32-bit data line. The Figure 5， RAM_R_W = （CPU_RAM_ strobe） & 6（CPU_WD） when RAM_R_W effective， C

21、PU_ write DATA through the tri-state gate output to RAM_DATA. When the CPU reads the RAM， the RAM data output by the gate circuit to the input terminal of the latch， wait for the CPU to read the data the walk （CPU_R_ latch signal after the data is stable by “CPU_R_ latch“ the data is latched on the

22、latch = （/ CPU_RD） & CPU_RAM_ strobe & 25MHz （/ 50 MHz） ） ）. Similarly within T0 period of the RAM corresponding data signal by “LCD_ latched“ 32-bit data locks exist on the latch. “LCD_ toner output latch signal in the appropriate moment in the corresponding T0-T3 cycle from T0-T3 select the corres

23、ponding 8-bit data output to the toner circuit this pixel data latch by TFT_LCD， read this tricolor data point and displayed. 3 Conclusions The actual performance test and environment test results show that， the controller design scheme is implemented by FPGA TFT - LCD digital display that have disp

24、lay effect and good compatibility system. According to the actual engineering requirements， a set of tailor-made display control scheme can effectively solve the practical problems of special LCD control chip that is not suitable for special occasions. In addition， the FGPA implementation of LCD dig

25、ital display control IP 7core， has the characteristics of abundant interface， occupying less system resources， portability， can be easily integrated into various types of LCD display system， have good application value. Reference 1 hang li， Liu Jianping， Hao Da. In the control circuit of AM-OLED dou

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