Layout Design and Verification of the Voltage Reference Module in the Auto Electronic Ignition Contr.doc

1、1Layout Design and Verification of the Voltage Reference Module in the Auto Electronic Ignition ContrAbstract： This article describes the layout design and verification of the input module of a auto electronic ignition chip used in the field of automotive engineering. Using standard bipolar technolo

2、gy， full-custom design on the input module placement and routing， and completed the back-end verification. This chip has low power consumption， low cost， and stable performance. Key words： Auto electronic ignition chip， Layout design 1 Introduction Auto electronic ignition control chip is designed f

3、or non-contact Hall effect tube ignition system. The chip is driving an external NPN Darlington tube to control the ignition coil， obtaining a sufficient ignition energy， accompanied by only a small energy loss. The design of auto electronic ignition control chip contains 10 modules： The reference v

4、oltage module， hall input circuit module， overvoltage protection circuit module， dwell control circuit module， current limit circuit module， control switch circuit module， slow recovery 2circuit module， desaturation sense circuit module， permanent conduction protection circuit module， driving circui

5、t module and RPM circuit module. This article focuses on the detailed analysis for the input module：， including the reference voltage module and Hall-effect transistor module after the completion of the system design and circuit design， simulationing， and then complete the back-end design 1 as well

6、as verification. The device used in this article circuit are all bipolar devices， using 5 micron standard bipolar process. Because the overall circuit of the chip is very large， so the circuit is divided into several modules to design， Design approximate location of each module in the device before

7、the first planned， Given package structure according to the process line to adjust the position of each module devices and pads after the whole layout. This design gives the package shown in Figure 1. 2 Circuit analysis， Simulation results and Layout design （1） The reference voltage module Functiona

8、l Analysis： When V3 begin supply to the entire circuit， with the the V3 elevated， Q58 conduction first， so Q60 conduction， Q57， Q58 constitute a Darlington transistor. 3As Q60 conduction， making the mirror current source Q59-1 and Q59-2 conduction， to supply the Bandgap reference composition of the

9、Q56，Q53 and R33， and finally a 1.25V reference voltage is generated at the base electrode of the Q38. After the reference voltage generator， the electric potential of base electrode of the Q61 is about 1.9V， which is higher than the Q60 B pole potential （1.4V） ， Therefore， Q60 close. R31，Q57，Q58，Q60

10、 form a starting circuit of the reference voltage. The simulation results can be seen， the design basically reach the required performance of the reference voltage module at 800 ， the output voltage of about 1.25V. The key components in the reference voltage module： The area ratio should strictly ma

11、tch of Q53 and Q56， the size of R33 affect the reference voltage value. R27，R28 should strictly match. The layout design of the reference voltage module： According to the tank to divide the standard cells， the transistors of the same collector potential can be placed in an isolated area. So the refe

12、rence voltage module circuit is divided into 10 isolated areas. Then to design devices in each isolated areas. 1. Design of the transistors 4The design of the chip should not only consider the performance of the circuit， but also consider the chip area， To try to make the minimum size of each device

13、， Adjust the size of the transistor first. Although the size of the transistor is adjusted to the minimum， will increase the series resistance of the device and increase the time constant， but can reduce the chip area， Balance， the benefits of shrinking device sizes far greater than the harm it brin

14、gs7. For the layout design of transistors， we must design a minimum size transistor first， this transistor is given according to the level of technology of the process line， the emitter area of the minimum size transistor is 1414in this design， then consider the minimum spacing on this basis， gradua

15、lly sets of synthetic a minimum size transistor， which is the standard transistor. According to the simulation of the circuit， calculates all the transistor emitter circuit size. Unit tube as the standard， calculates the emission area are N times the unit tube. Then according to the design rules ， l

16、ayout each transistor. In addition to the area of strict matching of the transistor， the emitter area and shape must be strictly 5consistent， and close to the place. Design of horizontal PNP tube sometimes uses split collector， single horizontal PNP transistor is divided into several smaller， common

17、 emitter， This can effectively reduce the transistor area， As long as the collector of same shape， and are symmetrically placed， the difference is within 1%8. 2. Design of resistance According to the resistance of different type has different sheet resistance， The large resistance is designed of inj

18、ection resistance， the small resistance is designed of diffusion resistance， the larger resistance is designed of an interlayer resistance. According to the end process line and layout correction factor determined resistance shape and corner number. There are 15 resistance in the module， through cal

19、culation and analysis， one is the base diffusion resistance， the rest is the injected resistance. 3. Design of Capacitor There is only one capacitor in this module， we can calculate its area： To calculate the area of capacitor ，we design this 6capacitor asa comb capacitor， The overlapping area of P

20、and N is 5000 ， to meet the requirement for the 2pF capacitance value. After designing of each device in the module， low risk and rules can be combined to reduce area. Voltage reference module layout design as shown in figure 4. 3 Layout Verification Universal integrated circuit is basal designed by

21、 artificial at present， and because of the electrical properties and process conditions constraints automatic layout design can not get satisfactory results at a time， it often needs engineering modification and supplement wiring. Because of the intervention of artificial land inevitably there will

22、be some mistake. On the other hand， Because of many physical factors， compared with the logic design， circuit design results， there will be some changes， therefore it is necessary to check the layout and verification. Including DRC， ERC， LVS and so on. In this design， the layout were checked by DRC

23、and LVS verification. DRC ensures the integrity of the layout design rule， LVS guarantees the consistency of the layout and circuit. 74 Conclusion The design of electronic ignition control chip success， to fill the gaps in the domestic similar chip design， the chip occupies smaller area， lower power

24、 consumption， so as to improve the utilization of the chip， save design cost. Reference literature 1 Chen Yun. Research LSI automatic layout design method D： Master thesis. Chengdu： University of Electronic Science and Technology， 2003 2 Chen Jinsong. Analog Integrated Circuits （theory， design， appl

25、ication） M. Beijing： China University of Science and Technology Press， 1997.93 115 3 P.R.Gray， R.G.Meyer. Analysis and Design of Analog Integrated Circuit M. 4th edition. Zhang Xiaolin translation. Beijing： Higher Education Press， 2003.240 248 4 Huang Zhen. Bipolar current-mode pulse width modulator

26、 Research and Design D： Master thesis. Xian： Xian University of Electronic Science and Technology， 2007 5 Zhao Lu. Protection circuit for a power management chip designs D： Master thesis. Chengdu： University of Electronic Science and Technology， 2007 6 Jiren Yuan，Christer Svensson. Principle of CMOS

27、 8Circuit Power-Delay Optimization with Transistor SizingJ. Circuits and Systems，1996.ISCAS “96，Connecting the World”，1996 IEEE International Symposium on Volume 1，12-15 May 1996： 637640 7 Bradley S.Carlson，Suh-Juch Lee. Delay Optimization of Digital CMOS VLSI Circuit by Transistor ReorderingJ. IEEE Transactions on Computer-Aided Design of Integrated Circuits and System，1995，Vol.14（10）： 11831192 8C.Toumazou，F.J.Lidgey，D.G.Haigh. Analogue IC Design： The Current-Mode ApproachM（London： Peternal Peter Peregrinus）1990： 250