The Front―end Design of high―resolution Video Communication System based on SoPC.doc

1、1The Frontend Design of highresolution Video Communication System based on SoPCAbstract： Using high-resolution CCD chip and high-speed A/D converter chip， the design of the Video Communication System is given in this article， which successfully realizes the drive of the high-resolution area CCD and

2、achieves the digital image signal. Based on the thought of SoPCs （System on Programmable Chip） high integration， on the ALTERA companys DE2 platform， FPGA is used to achieve the driving timing of CCD， Silicon delay lines are used to properly align the pixel rate CCD clock signals with respect to one

3、 another， and the push-pull transistor circuits are designed to translate TTL level driving clock signal to the voltage levels required by the CCD. The system demonstrates some application values by analysis. Key words： Video Capture System； System on Programmable Chip（SoPC） ；Charge Coupled Devices（

4、CCD ） ； Area CCD Driving； A/D Conversion 1 Introduction The rapid development of microelectronic technique not only 2makes integration level of devices is higher and higher， but also promotes the emergence and development of SoC（System on Chip）. SoC uses IP（Intellectual Property）core as design basis

5、. Starting from the perspective of the whole system， it integrates settlement mechanism， model algorithm， chip architecture and device design closely 1. SoC makes full uses of the existing design， which not only evidently reduces design cycle， but also improves design capability of ASIC. So it devel

6、ops rapidly. SoPC technique is a flexible and high-efficiency SoC solution which was firstly proposed by Altera Corporation in 2000. It integrates the function modules for system design including professor， storage， I/O port， LVDS and CDR into a device， which establishes a programmable SoC. It has f

7、lexible design approach， and it can be clipped， upgraded and extended. And it has the function that software and hardware can be programmable in the system. With the development of modern communication technology and operation， the requirements on communication has transformed into combination of vo

8、ice， data and video from single voice communication. And it has been applied to high-definition video communication system. Applying SoPC technique to realize front control of video communication system has the advantages of 3flexible design， low cost， easy external circuitry and convenient maintena

9、nce. Therefore， the paper analyzes techniques based on SoPC， and applies multiple IP cores and the existing software system to realize front design of video communication system. 2 System Design 2.1 System architecture design The system is the front design of video communication system based on SoPc

10、. It consists of CCD sensor， CCD drive signal level monitoring circuit， CCD drive signal delay circuit， CCD video signal A/D conversion， FPGA generating driving schedules and controlling signals， SDRAM caching CCD image data and controller for data dissemination. The particularity of CCD output sign

11、al which means that there are useless signals periodically requires that the time for A/D conversion needs to be controlled. ADC with CDS function is applied in the paper. And the control on CDS must be synchronous with CCD driving schedules. According to actual requirements of data acquisition in h

12、igh-resolution video communication， the system uses KAF-8300 CCD sensor produced in Kodak Corporation as photovoltaic conversion equipment. It is a monochrome array CCD with high performance， and the total number of pixels is 8.3 million. 4And it has the characteristics of high resolution， high dyna

13、mic range and low noise. The function of analog-to-digital conversion is to convert effective analog signals which are output by CCD into digital signals to composite， convert， analyze and process trailing images. It may influence signal to noise ratio of the system， bandwidth and image steadiness，

14、so it is the key to performance of video communication system. AD9845 of ADI Corporation is a high-speed ADC with the function of processing signals of CCD. The internal register is configured by a tri-linear serial data bus. In order to make CCD horizontal drive signal， RESET CLOCK， ADC control sam

15、pling signal and sample clock match with timing sequence of output pixels， the signals must receive accurate delayed time process. Programmable chip delay line DS1021S-25 of Mission Company is used to make delay process on the signals. The driving signals provided by FPGA and delay line IC cant be d

16、irectly provided for CCD， and they need level conversion. The design in the paper selects MAX4427 and high-speed transistor of MAXIM Company to realize level conversion. The development platform is DE2 development board of Altera Company. DE2 not only provides various devices and multimedia features

17、 for users， but also has flexible and reliable peripheral interface 5design. 2.2 SoPc development design Altera uses SoPC development of Nios II processor. The design of SoPC developing hardware is based on SoPC development environment， SoPC Builder. SoPC Builder can be seen as a tool using IP modul

18、e as input and using integrated system as output. Under the environment， the processor， IP core and user logic can be added easily. And the modules can be connected by Avalon bus. SoPC Builder will generate HDL description of system modules. 2.3 CCD driving schedule design Kodak KAF-8300 used in the

19、 paper is（FF）CCD. It includes a concurrent CCD shift register， a serial CCD shift register and a signal output amplifier. The driving signals of KAF-8300 include V1， V2， H1， H1L， H2 and RG 1. The signals are synchronous with master clock， and can be realized by counting master clock. V1and V2 is dri

20、ving signal of vertical clock， H1， H1L and H2 are driving signals of horizontal clock， and RG is reset signal. If the process of CCD outputting a frame of image is used as a work cycle， each work cycle includes Flush， INTEGRATE， V_TRANSFER and H_TRANSFER. Separately designing the working conditions

21、is helpful to design simplified driving schedules. In order to achieve high-quality 6image signals， after transmitting a frame of images， CCD needs to be refreshed to remove the non-transmitted electric charges. The method of realizing refresh operation is to input several vertical clocks， V1 and V2

22、. Integration operation sequences 4 required by CCD are as follows. At the beginning of integration operation， two integrations refer to delay of clock period before heightening integration synchronous signals. After integration time is up， two integration reference clock period needs to be delayed

23、until the next step. From working principle of（FF）CCD， we can see that integration charge of CCD is firstly transferred into horizontal register. And the horizontal clock must stop. Vertical signal V1 and V2 are controlled by counting pixel clock. After the above vertical transition， CCD electric ch

24、arge needs to be transferred from horizontal register to output structure of CCD pixel by pixel. It is similar to vertical clock， and horizontal transition sequence is realized by using counter. And controlling signal SHP and SHD of CCD for AD9845 need to be generated. While CCD driving signal seque

25、nce is generated， FPGA needs to generate controlling signals for each module of the system， which coordinates each module. The controlling signals include initialized serial bus signal on 7ADC and driving signal delay circuit， ADC sampling signal， pixel clock of CCD image， line synchronizing signal，

26、 field-synchronizing signal and CCD light integral signal. In order to realize the above controlling signals and CCD driving sequence， the design uses state machine in Figure 1. After pressing reset key， firstly， the counters in FPGA need to be reset in POWER ON/BORD RESET state. Then， working mode

27、is selected in CLEAR and SETUP state. If it is digital still camera， it needs to wait for the generation of external triggering signals. If it is common operation mode， it needs to directly enter CCD refresh operation. If it is idle operation mode， the refresh operation is skipped and CCD driving si

28、gnal is directly generated. And CCD video signal is output. After the output of a frame of images is completed， the internal counter operation is reset for the output of the next frame of images. 2.4 Design of delay process and level conversion of CCD driving signals In order to make CCD driving sig

29、nals including H1， H1BR， H2 and H2BR， reset clock， ADC control sampling signal and sampling signal match with output pixel sequences， the signals must receive accurate delay process. Programmable delay line chip DS1021S-25 of Mission Company is used to make delay 8process on the signals. Delay time

30、=10.0+0.25（the written data） （ns）. FPGA outputs LVTTL signal of 3.3V. Delay line IC outputs TTL signal of 5V， which cant meet driving signal level required by CCD 2. The frequency of vertical signal V1 and V2 is only 7.6KHz， so the level conversion is easy compared with H1，H1L， H2 and H2L with the f

31、requency of 28MHz. And MOSFET can be used. The specific practice is to connect VDD pin of MOSFET with the required high level， and to connect GND pin with the required low level. The value of high and low level can be changed by two potentiometers. The design uses MOSFET which is MAX4427 of MAXIM Co

32、mpany. The chip is MOSFET driver with high-speed 1.5A rated current. And MOSFET cant be used for implementation. High-speed transistor is used to realize conversion of high and low level. And high and low level can be changed by two potentiometers. 2.5 CCD output signal process and A/D quantization

33、The output stage of CCD converts inductive charge generated by each pixel into voltage by capacitor Cg. In the beginning of each pixel cycle， the voltage of Cg is reset to reference level VREF to make reset peak pulse emerge. The effective value of optical signal felt by each pixel is represented by

34、 9V（referring to the difference of level and video voltage）. The output signal of CCD is very small and is hidden in noise， so CDS circuit is generally used. 3 Result Analysis 3.1 FPGA output driving sequence signal KAF-8300 needs sequence signals. H1， H2 and H1L are signals of 28MHz. There are 3448

35、 H pulse signals between two V1（V2） pulses. And the wave display used to observe phase. 3.2 Driving signals and CCD output signals after level adjustment Driving signals after level adjustment achieves the indexes required by CCD， high level 2.6V low level -9.25V and of V1 and V2， high and low level

36、 H1（1.5，-4.5） ，H2（1，5） and H1L（1.5，-6.5） of horizontal signal. High level of RG is required to reach 8V， and low level is required to reach 2V. Video signals and reference level are ideal， and drive circuit achieves the design objective. 3.3 A/D conversion test A/D conversion test is used to test if

37、 AD9845 operates normally. Firstly， oscilloscope is used to test controlling clock signal of AD9845. The signals include master sampling clock DATACLK， CDS sampling clock SHP and SHD， PBLK， CLPOB and CLPDM. The test results indicate that the clock signals can 10meet the requirements. Testing if AFE

38、can operate CDS and ADC needs to estimate the characteristics of AFE output data. And it is impossible to directly load CCD driving signal. Therefore， the design loads square signals with the frequency of 3MHz and amplitude of 2V which is generated by EE1411-type composite function signal generator

39、to input side of analogue signal of AD9845. The sampling clock of AD9845 is 28MHz. If AD9845 operates correctly， the result of A/D conversion is 4 or 5 maximum values closing to 0xFFF， or 4 or 5 minimum values closing to 0. The result of A/D conversion is transmitted to the results of PC by USB， as

40、shown in Figure 2. The results indicate that AD9845 can make A/D conversion. The converted data receives rational data compression algorithm， and is transmitted to the remote end by transmitting control interface， for realizing processing the front-end data of video communication system. 4 Conclusio

41、n The paper studies acquisition and quantization of front-end data of video communication system. The paper uses the design SoPC programmable system， which improves integration and reliability greatly and is easy for miniaturization of the system. The image acquisition uses high-performance CCD chip