中国科学院深圳先进技术研究院导师简况表.DOC

1、中国科学院深圳先进技术研究院导师简况表 导师姓名 麦穗冬 性别 男 职称 研究员 专业名称 电子工程学 导师类别 博导 硕导 所在单元 广州中国科学院先进技术研究所 是否兼职 是 否 招生专业 物理化学（含化学物理）生物化学与分子生物学信号与信息处理模式识别与智能系统计算机应用技术材料工程 电子与通信工程控制工程 计算机技术生物工程 研究方向 多核和嵌入式系统设计 (片上网络 , FPGA, 片上多核处理器 ) 高性能生物计算系统 (网 络药 理学和 药 物 发现 , 生物信息 学 计 算系 统 ) 脑机接口 (脑植入式系统 , 闭环动态夹紧 系 统 ) 新兴技术 (3-D 大规模集成技术 ,

2、 能量获取电路 , 动态可编程网络 ) 在研课题 独立项目： 青年千人计划研究经费 9/2012 合作项目： 能量自适应可重构系统建模及控制算法 中国国家自然科学基金委资助 , 2012 年 1 月 独立项目： Networked-Processors for Complex Network-based Drug Discovery Supported by UK Technology Strategy Board, granted since 7/2011 独立项目： Dynamic Programming Networks for 3-D VLSI System Integration S

3、upported by Royal Society granted since 5/2011 独立项目： Visiting fellowship for collaboration Support by HiPEAC, European Research Council, 5/2011 独立项目： Champion of Neurally-Inspired Engineering SIG for UK Neuroinformatic Group Supported by UK Research Council (EPSRC, BBSRC), granted since 4/2011 个人简历

4、工作经历 012.09-至今 : 主任， 智能芯片及系统中心， 广州中国科学院先进技术研究所 2010.03-2012.08：副教授， 电子与计算机工系讲师 ， 纽卡斯尔大学（英国） 2008.10-2009.02：研究员， 太阳微系统实验室（美国） 2004.02-2009.02：访问科学家， 麻省理工学院（美国） 教育经历 2005.09-2009.12：博士， 电子与电气工程， 英国帝国理工学院 2003.09-2005.06：硕士生， 系统工程专业硕士， 香港中文大学 2000.09-2003.06：本科生， 香港中文大学 主要科研成果及所获荣誉 文章： 1. Terrence Mak

5、, Truncation Error Analysis of MTBF Computation for Multi-Latch Synchronisers, Elsevier, Microelectronics Journal, 2011 SCI Index：WOS:000301751000009, IDS Number: 911WD 2. Terrence Mak, Kai-Pui Lam, Peter Y.K. Cheung, Wayne Luk, “Adaptive Routing for Network-on-Chips Using a Dynamic Programming Netw

6、ork”, IEEE Trans. Industrial Electronics, Vol. 58, no. 8, pp. 3701-3716, 2011 SCI Index: WOS:000293685700056, IDS Number: 804WT 3. Terrence Mak, Kai-Pui Lam, H.S. Ng, Guy Rachmuth, Chi-Sang Poon, “A CMOS Current-Mode Dynamic Programming Circuit”, IEEE Trans. Circuits and Systems I, Vol. 57, no. 22,

7、pp. 3112-3123, 2010 SCI Index: WOS: 000285361200010, IDS Number: 695HM 4. Terrence Mak, Pete Sedcole, Peter Y.K. Cheung and Wayne Luk, “Average Interconnections Delay Estimation for On-FPGA Communication Links”, IET Electronics Letters, Vol. 43, No. 17, pp 918-920, 2007 SCI Index: WOS:00024928220000

8、9, IDS Number: 207WQ 5. Terrence Mak, G. Rachmuth, K.P. Lam, and C-S. Poon, “A Component-based FPGA Design Framework for Neuronal Ion Channel Dynamics Simulations”, IEEE Trans. Neural Systems & Rehabilitation Engineering, Vol.14, No.4, pp 410-418, 2006 SCI Index: WOS:000249282200009, IDS Number: 207

9、WQ 6. Terrence Mak, K. P. Lam, “Equivalence - Set Genes Partitioning Using an Evolutionary - DP Approach”, IEEE Trans. NanoBioscience, Vol. 4, No. 4, pp 295-300, 2005 SCI Index: WOS:000233757200004 , IDS Number: 990QB 7. Terrence Mak, Chi-Sang Poon (Guest Editors), Special Issue: 3-D VLSI Systems In

10、tegration, the Computer Journal, Oxford Journal, 2011 8. Terrence Mak, Raaed Al-Dujaily, Kuan Zhou, Kai-Pui Lam, Chi-Sang Poon, “3-D On-Chip Dynamic Programming Network Using TSV-based Technology”, IEEE Circuits and Systems Magazine, Vol. 11, no. 3, 51-62, 2011 9. Terrence Mak, Pete Sedcole, Peter Y

11、.K. Cheung, Wayne Luk, “Global Communication in FPGAs Using Wave-Pipelined Signalling”, Elsevier, Integration, the VLSI Journal, Vol. 43, No. 2, pp188-201, 2010 EI: 11303669 10. Bo Yu, Terrence Mak, Xiangyu Li, Leslie Smith, Yihe Sun and Chi-Sang Poon, Stream-based Hebbian Eigenfilter for Real-Time

12、Neuronal Spike Discrimination, BioMedical Engineering OnLine, vol. 11, no. 18, 2012 SCI Index：WOS:000304062800001, IDS Number: 942QT 11. Raaed Al-Dujaily, Terrence Mak, Fei Xia, Alex Yakovlev and Maurizio Palesi, Embedded Transitive Closure Networks for Run-Time Deadlock Detection in Networks-on-Chi

13、p, IEEE Trans. Distributed and Parallel Systems, 2012 SCI Index：WOS:000304413700004, IDS Number: 947FJ 12. Bo Yu, H. M. Chan, Terrence Mak, Y. Sun, Chi-Sang Poon, On-Chip Systolic Networks for Real-Time Tracking of Neural Correlation Networks, (accepted) IEEE Trans. on Biomedical Engineering 13. Raa

14、ed Al-Dujaily, Terrence Mak, Kai-Pui Lam, Fei Xia, Alex Yakovlev, Chi-Sang Poon, Dynamic On-Chip Thermal Optimization for 3D Networks-on-Chip, (accepted) The Computer Journal 14. Bo Yu, Terrence Mak, Xiangyu Li, Fei Xia, Alex Yakovlev, Yihe Sun, Chi-Sang Poon, Real-Time FPGA-Based Multi-Channel Spik

15、e Sorting Using Hebbian Eigenfilter, (to appear) IEEE Journal on Emerging and Selected Topics in Circuits and Systems: Brain-Machine Interface, 2012 15. Ghaith Tarawneh, Terrence Mak, Alex Yakovlev, Computational Models for Metastability Failure Rates in ADCs, (under review) IEEE Trans. Circuits and

16、 Systems I 16. Raaed Al-Dujaily, Terrence Mak, Kai-Pui Lam, Chi-Sang Poon, Dynamic Thermal Optimization in 3-D Networks-on-Chip, (under review) The Computer Journal 获奖 : 中组部“青年千人”， 2012 香港中文大学工程学 院杰出校友 , 2011 Premier International Conference on Design, Automation and Test in Europe (DATE)最佳论文奖 (与会 8

17、00 余篇论文中唯一获奖论文 ), 4/2011 裘槎基金会奖学金 , 2005-2008 美国海军研究办公室神经工程领域杰出贡献奖 , 2005 其他 教学任务： Since 3/2010 Electronics (II) EEE2006: 二年级本科生核心课程 Projects EEE1004: 一年级本科生核心课程 Digital Electronics - EE2: 二年级本科生核心课程 协助指导研究生 ： Since 3/2010 指导 1 名研究助理 , 6 名博士生 , 4 名初级研究助理 指导两人完成博士论文： Robin Emery, 论文题目 : Reconfigurabl

18、e VLSI System for Large-Scale Dynamics Neuronal Network Modeling, 纽卡斯尔大学 , 2010 Panos Asimakopoulos, 论文 题目 : Characterization and Optimization of 3-D TSV-based VLSI Systems, 纽卡斯尔大学 , 2011 联系方式 邮箱 电话 14714612074， 020-22912746， +85298773391 个人主页 http:/www.cse.cuhk.edu.hk/stmak/News.html 备注 Name Terre

19、nce Mak Positions Researcher Academic title Ph.D. E-mail Phone 14714612074 020-22912746 +85298773391 Personal Website http:/www.cse.cuhk.edu.hk/stmak/News.html Resume Current Appointments The Chinese University of Hong Kong, Hong Kong Since 8/2012 Department of Computer Science and Engineering Assi

20、stant Professor Newcastle University, UK Since 3/2010 8/2012 School of Electrical, Electronic and Computer Engineering (EECE) Lecturer (equivalent to Assistant Professor) Institute of Neuroscience (IoN), Newcastle Biomedicine Affiliated Lecturer Massachusetts Institute of Technology, USA Since 8/201

21、1 Harvard-MIT Health Sciences and Technology Visiting Scientist (supported by The Royal Society) Education Imperial College London, UK 12/2009 PhD in Electrical and Electronic Engineering, co-supervised by Prof. Peter Cheung and Prof. Wayne Luk Thesis: Circuit Design and Analysis for On-Chip Communi

22、cation Systems The Chinese University of Hong Kong, Hong Kong 8/2005 BEng and MPhil in Systems Engineering, supervised by Prof. Kai-Pui Lam Thesis: High-Performance Reconfigurable Computing for Biomedical Applications Previous Appointments Research scientist 2008-2009 Sun Microsystems Laboratories,

23、Menlo Park, USA, supervised by Turing laureate Prof. Ivan Sutherland Research student 2004-2005 Harvard-MIT Health Sciences and Technology, MIT, supervised by Dr. Chi-Sang Poon Direction Multi-core and embedded systems and design (Networks-on-Chip, FPGAs, Chip Multi-Processors) High-performance bio-

24、computing systems (networked pharmacology and drug discovery, bioinformatics computing systems) Brain-machine interface (hardware efficient spike sorting, 3-D heterogeneous integration for implantable systems, closed-loop dynamic clamping systems) Emerging technologies (3-D VLSI integration, Energy

25、harvesting circuits, dynamic programming networks) Achievements The National Youth thousands plan in 2012 Piloting internationally leading research on Multi-Core Systems Design, Bio-Embedded- Computing and Brain-machine Interface Systems Awarded multiple research grants from the UK research councils

26、 including UK-EPSRC, TSB, EU-FP7 and NSFC Awarded the Croucher Foundation Scholarship and the Best Paper Award at DATE2011 Strong publication record, including 11 peered-reviewed journals and 33 conference proceedings Extensive collaboration network, including MIT, Imperial College, Tsinghua Univers

27、ity, UEST China and industrial partners, including Oracle, Intel, e-Therapeutics PLC Article 1. Terrence Mak, Truncation Error Analysis of MTBF Computation for Multi-Latch Synchronisers, Elsevier, Microelectronics Journal, 2011 SCI Index：WOS:000301751000009, IDS Number: 911WD 2. Terrence Mak, Kai-Pu

28、i Lam, Peter Y.K. Cheung, Wayne Luk, “Adaptive Routing for Network-on-Chips Using a Dynamic Programming Network”, IEEE Trans. Industrial Electronics, Vol. 58, no. 8, pp. 3701-3716, 2011 SCI Index: WOS:000293685700056, IDS Number: 804WT 3. Terrence Mak, Kai-Pui Lam, H.S. Ng, Guy Rachmuth, Chi-Sang Po

29、on, “A CMOS Current-Mode Dynamic Programming Circuit”, IEEE Trans. Circuits and Systems I, Vol. 57, no. 22, pp. 3112-3123, 2010 SCI Index: WOS: 000285361200010, IDS Number: 695HM 4. Terrence Mak, Pete Sedcole, Peter Y.K. Cheung and Wayne Luk, “Average Interconnections Delay Estimation for On-FPGA Co

30、mmunication Links”, IET Electronics Letters, Vol. 43, No. 17, pp 918-920, 2007 SCI Index: WOS:000249282200009, IDS Number: 207WQ 5. Terrence Mak, G. Rachmuth, K.P. Lam, and C-S. Poon, “A Component-based FPGA Design Framework for Neuronal Ion Channel Dynamics Simulations”, IEEE Trans. Neural Systems

31、& Rehabilitation Engineering, Vol.14, No.4, pp 410-418, 2006 SCI Index: WOS:000249282200009, IDS Number: 207WQ 6. Terrence Mak, K. P. Lam, “Equivalence - Set Genes Partitioning Using an Evolutionary - DP Approach”, IEEE Trans. NanoBioscience, Vol. 4, No. 4, pp 295-300, 2005 SCI Index: WOS:0002337572

32、00004 , IDS Number: 990QB 7. Terrence Mak, Chi-Sang Poon (Guest Editors), Special Issue: 3-D VLSI Systems Integration, the Computer Journal, Oxford Journal, 2011 8. Terrence Mak, Raaed Al-Dujaily, Kuan Zhou, Kai-Pui Lam, Chi-Sang Poon, “3-D On-Chip Dynamic Programming Network Using TSV-based Technol

33、ogy”, IEEE Circuits and Systems Magazine, Vol. 11, no. 3, 51-62, 2011 9. Terrence Mak, Pete Sedcole, Peter Y.K. Cheung, Wayne Luk, “Global Communication in FPGAs Using Wave-Pipelined Signalling”, Elsevier, Integration, the VLSI Journal, Vol. 43, No. 2, pp188-201, 2010 EI: 11303669 10. Bo Yu, Terrenc

34、e Mak, Xiangyu Li, Leslie Smith, Yihe Sun and Chi-Sang Poon, Stream-based Hebbian Eigenfilter for Real-Time Neuronal Spike Discrimination, BioMedical Engineering OnLine, vol. 11, no. 18, 2012 SCI Index：WOS:000304062800001, IDS Number: 942QT 11. Raaed Al-Dujaily, Terrence Mak, Fei Xia, Alex Yakovlev

35、and Maurizio Palesi, Embedded Transitive Closure Networks for Run-Time Deadlock Detection in Networks-on-Chip, IEEE Trans. Distributed and Parallel Systems, 2012 SCI Index：WOS:000304413700004, IDS Number: 947FJ 12. Bo Yu, H. M. Chan, Terrence Mak, Y. Sun, Chi-Sang Poon, On-Chip Systolic Networks for

36、 Real-Time Tracking of Neural Correlation Networks, (accepted) IEEE Trans. on Biomedical Engineering 13. Raaed Al-Dujaily, Terrence Mak, Kai-Pui Lam, Fei Xia, Alex Yakovlev, Chi-Sang Poon, Dynamic On-Chip Thermal Optimization for 3D Networks-on-Chip, (accepted) The Computer Journal 14. Bo Yu, Terren

37、ce Mak, Xiangyu Li, Fei Xia, Alex Yakovlev, Yihe Sun, Chi-Sang Poon, Real-Time FPGA-Based Multi-Channel Spike Sorting Using Hebbian Eigenfilter, (to appear) IEEE Journal on Emerging and Selected Topics in Circuits and Systems: Brain-Machine Interface, 2012 15. Ghaith Tarawneh, Terrence Mak, Alex Yakovlev, Computational Models for Metastability Failure Rates in ADCs, (under review) IEEE Trans. Circuits and Systems I 16. Raaed Al-Dujaily, Terrence Mak, Kai-Pui Lam, Chi-Sang Poon, Dynamic Thermal Optimization in 3-D Networks-on-Chip, (under review) The Computer Journal