状态机作业8-3 根据图8-32(a) ，按照图8-32(b) 写出对应结构的 Verilog HDL 状态机。module fsmb ( CLK, rese,ina, outa); input CLK,reset; input ina; output outa; reg outa; reg1:0 c_state; parameter1:0 st0 = 0; parameter1:0 st1 = 1; parameter1:0 st2 = 2; parameter1:0 st3 = 3; always (posedge CLK or negedge reset) ) begin : if (!reset) c_state = st0; else begin case (c_state) st0 : begin if (ina = 3b101 ) outa =4b0010 ; else if ina = 3b111 outa = 4b1100 ; c_state = st1 ; endst1 : begin outa = 4b1001 ; if (ina = 3b000) begin c
