精选优质文档-倾情为你奉上Assignment 91. Design an 8-bit up and down synchronous counter in VHDL with the following features:(1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state).(2) The counter is with an asynchronous reset that assigns a specific initial value for counting.(3) The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counti
