Verilog实现的8位超前进位加法器(共2页).doc

精选优质文档-倾情为你奉上Verilog实现的8位超前进位加法器。经过modelsim验证正确可用，在DC下综合成功/文件名：add_8.v/模块名：add_8/timescale 1ns/1nsmodule add_8 ( input 7:0a, input 7:0b, input cin, output 7:0 s, output co );wire 7:0c_tmp;wire 7:0g;wire 7:0p;assign co = c_tmp7;assign g0 = a0 & b0,g1 = a1 & b1,g2 = a2 & b2,g3 = a3 & b3,g4 = a4 & b4,g5 = a5 & b5,g6 = a6 & b6,g7 = a7 & b7;assign p0 = a0 | b0