1、习题二、四位乘法器的设计 问题说明： 每个学生根据自己的对于乘法运算和乘法器设计的理解，进行乘法器电路的设计，并用 FPGA 实现之。仅要求能够实现四位 BIT 的乘法运算，其他不作约束，根据自己的理解和兴趣，自由定义。 设计实验要求： 1各自自行定义和设计，互相要有差异化，说明自己的定义特征和设计思想,要求设计至少一种电路去实现. 2对于自行设计有特色和原理说明详细的实验，即使实现结果有局部错误，也给予高分评价。 3要求设计实验报告内容包括：设计定义说明、电路图、功能仿真和时序仿真图、实现后的有关资源利用等 REPORT 文件内容摘要。图为：四位乘法器一个数的高四位与另一个数的低两位乘累加器
2、图为：一位全加器图为：四位乘法器一个数的高四位与另一个数的高两位乘累加器图为 ：将四位二进制乘数与低两位二进制数相乘累加结果与另一组四位二进制乘数与高两位二进制数相乘累加结果进行相加，最后计算出四位与四位相乘的结果。功能仿真结果：通过原理图的输入，后经过功能上的仿真输出了以下原理图 VHDL 的功能实现代码。library ieee;use ieee.std_logic_1164.ALL;use ieee.numeric_std.ALL;- synopsys translate_offlibrary UNISIM;use UNISIM.Vcomponents.ALL;- synopsys tr
3、anslate_onentity four_bit_mul3 isport ( a0 : in std_logic; a1 : in std_logic; a2 : in std_logic; a3 : in std_logic; b0 : in std_logic; b1 : in std_logic; b2 : in std_logic; b3 : in std_logic; clk : in std_logic; clr : in std_logic; S1 : out std_logic; s2 : out std_logic; s3 : out std_logic; s4 : out
4、 std_logic; s5 : out std_logic; s6 : out std_logic; s7 : out std_logic; s8 : out std_logic);end four_bit_mul3;architecture BEHAVIORAL of four_bit_mul3 isattribute BOX_TYPE : string ;signal XLXN_68 : std_logic;signal XLXN_101 : std_logic;signal XLXN_103 : std_logic;signal XLXN_104 : std_logic;signal
5、XLXN_105 : std_logic;signal XLXN_106 : std_logic;signal XLXN_107 : std_logic;signal XLXN_108 : std_logic;signal XLXN_109 : std_logic;signal XLXN_110 : std_logic;signal XLXN_119 : std_logic;signal XLXN_120 : std_logic;signal XLXN_129 : std_logic;signal XLXN_130 : std_logic;signal XLXN_131 : std_logic
6、;component fourbit_mulport ( clr : in std_logic; a3 : in std_logic; a2 : in std_logic; a1 : in std_logic; b0 : in std_logic; b1 : in std_logic; clk : in std_logic; a0 : in std_logic; out1 : out std_logic; out2 : out std_logic; add1 : out std_logic; add2 : out std_logic; add3 : out std_logic; add4 :
7、out std_logic);end component;component foutbit_mul1port ( clr : in std_logic; a1 : in std_logic; a0 : in std_logic; a2 : in std_logic; a3 : in std_logic; b2 : in std_logic; b3 : in std_logic; clk : in std_logic; add1_1 : out std_logic; add2_1 : out std_logic; add3_1 : out std_logic; out8 : out std_l
8、ogic; out9 : out std_logic; add4_1 : out std_logic);end component;component mulport ( A : in std_logic; B : in std_logic; Cin : in std_logic; S : out std_logic; Cout : out std_logic);end component;component GNDport ( G : out std_logic);end component;attribute BOX_TYPE of GND : component is “BLACK_BO
9、X“;beginXLXI_1 : fourbit_mulport map (a0=a0,a1=a1,a2=a2,a3=a3,b0=b0,b1=b1,clk=clk,clr=clr,add1=XLXN_101,add2=XLXN_105,add3=XLXN_107,add4=XLXN_110,out1=S1,out2=s2);XLXI_2 : foutbit_mul1port map (a0=a0,a1=a1,a2=a2,a3=a3,b2=b2,b3=b3,clk=clk,clr=clr,add1_1=XLXN_103,add2_1=XLXN_106,add3_1=XLXN_108,add4_1
10、=XLXN_119,out8=XLXN_129,out9=s8);XLXI_3 : mulport map (A=XLXN_101,B=XLXN_103,Cin=XLXN_68,Cout=XLXN_104,S=s3);XLXI_4 : mulport map (A=XLXN_105,B=XLXN_106,Cin=XLXN_104,Cout=XLXN_109,S=s4);XLXI_5 : mulport map (A=XLXN_107,B=XLXN_108,Cin=XLXN_109,Cout=XLXN_120,S=s5);XLXI_14 : GNDport map (G=XLXN_68);XLX
11、I_18 : mulport map (A=XLXN_110,B=XLXN_119,Cin=XLXN_120,Cout=XLXN_130,S=s6);XLXI_19 : mulport map (A=XLXN_130,B=XLXN_129,Cin=XLXN_131,Cout=open,S=s7);XLXI_21 : GNDport map (G=XLXN_131);end BEHAVIORAL;时序仿真：一位全加法器：四位与低两位乘法器：四位与高两位乘法器：最后结果：完整的综合仿真报告：Release 7.1i - xst H.38Copyright (c) 1995-2005 Xilinx,
12、 Inc. All rights reserved. Parameter TMPDIR set to _projnavCPU : 0.00 / 0.23 s | Elapsed : 0.00 / 0.00 s Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.23 s | Elapsed : 0.00 / 0.00 s Reading design: four_bit_mul3.prjTABLE OF CONTENTS1) Synthesis Options Summary2) HDL Compilation3) HDL Analysis4) HDL
13、 Synthesis5) Advanced HDL Synthesis5.1) HDL Synthesis Report6) Low Level Synthesis7) Final Report=* Synthesis Options Summary *=- Source ParametersInput File Name : “four_bit_mul3.prj“Input Format : mixedIgnore Synthesis Constraint File : NO- Target ParametersOutput File Name : “four_bit_mul3“Output
14、 Format : NGCTarget Device : acr2- Source OptionsTop Module Name : four_bit_mul3Automatic FSM Extraction : YESFSM Encoding Algorithm : AutoMux Extraction : YESResource Sharing : YES- Target OptionsAdd IO Buffers : YESEquivalent register Removal : YESMACRO Preserve : YESXOR Preserve : YES- General Op
15、tionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : YESRTL Output : YesHierarchy Separator : /Bus Delimiter : Case Specifier : maintain- Other Optionslso : four_bit_mul3.lsoverilog2001 : YESsafe_implementation : NoClock Enable : YESwysiwyg : NO=* HDL Compilation *=Compiling vhdl fi
16、le “E:/program work/multiplier/multiplier/mul.vhf“ in Library work.Architecture behavioral of Entity mul is up to date.Compiling vhdl file “E:/program work/multiplier/multiplier/fourbit_mul.vhf“ in Library work.Architecture behavioral of Entity fdc_mxilinx_fourbit_mul is up to date.Architecture beha
17、vioral of Entity fourbit_mul is up to date.Compiling vhdl file “E:/program work/multiplier/multiplier/foutbit_mul1.vhf“ in Library work.Architecture behavioral of Entity fdc_mxilinx_foutbit_mul1 is up to date.Architecture behavioral of Entity foutbit_mul1 is up to date.Compiling vhdl file “E:/progra
18、m work/multiplier/multiplier/four_bit_mul3.vhf“ in Library work.Architecture behavioral of Entity four_bit_mul3 is up to date.=* HDL Analysis *=Analyzing Entity (Architecture ).WARNING:Xst:753 - “E:/program work/multiplier/multiplier/four_bit_mul3.vhf“ line 180: Unconnected output port Cout of compo
19、nent mul.Entity analyzed. Unit generated.Analyzing Entity (Architecture ).Set user-defined property “HU_SET = XLXI_29_7“ for instance in unit .Set user-defined property “HU_SET = XLXI_30_6“ for instance in unit .Set user-defined property “HU_SET = XLXI_31_5“ for instance in unit .Set user-defined property “HU_SET = XLXI_32_4“ for instance in unit .Set user-defined property “HU_SET = XLXI_41_0“ for instance in unit .
