基于VHDL语言的数字钟设计.doc

一程序代码及其仿真：1 cnt60子模块代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY V_cnt60 ISPORT ( clk :IN std_logic; Q0,Q1,Q2,Q3,Q4,Q5,Q6,QC :OUT std_logic);END V_cnt60;ARCHITECTURE func OF V_cnt60 ISSIGNAL count1 :std_logic_vector(3 downto 0);SIGNAL count2 :std_logic_vector(3 downto 0);SIGNAL carryin:std_logic;BEGIN Q0 = count1(0); Q1 = count1(1); Q2 = count1(2); Q3 = count1(3); Q4 =