综合基本知识李晓明内容模块综合过程关键约束介绍约束文件实例DC 图形界面综合的过程Synthesis =residue = 16h0000;if (high_bits = 2b10) residue = state_tableindex;else state_tableindex = 16h0000;HDL SourceGeneric Boolean (GTECH)TranslateTarget TechnologyOptimize + MapTranslation + Optimization + MappingSynthesisIsConstraint-DrivenDesign Compiler 对设计进行优化，以达到你的设计目标LargeAreaSmallShort Delay High 设计者设定目标 (through constraints)write模块综合过程gtech.dbGTECH my_chip.v(hd)writeOPTIMIZATION + MAPPINGsourceDC_MEMORYTRANSLATIONscriptsconstraints.tclmapped
