1、University of Electronic Science and Technology of China Digital Logic circuit and systemDigital Design and Computer Architecture, 2nd EditionDavid Money Harris and Sarah L. HarrisChapter 1 From Zero to oneUniversity of Electronic Science and Technology of China Digital Logic circuit and systemChara
2、cteristic of CMOS gatesBOOK:C3 3.4, 3.5, 3.6, 3.7, 3.8References: C1-1.6 1.7 University of Electronic Science and Technology of China Digital Logic circuit and systemOutline CMOS逻辑电路特性 逻辑电平 噪声容限 扇入 /扇出 多余输入端的处理 动态特性：转换时间（上升沿 /下降沿），传输延迟 电流尖峰 /去耦电容 其他结构的逻辑电路 三态门 漏极开路门 传输门3/207 Electrical Not logicUniv
3、ersity of Electronic Science and Technology of China Digital Logic circuit and system54/74HC00 data sheetUniversity of Electronic Science and Technology of China Digital Logic circuit and systemCMOS Static Electrical BehaviorCMOS Static Behavior- “Static“ or “DC“ refers to the gates operation when t
4、he inputs are NOT changing- also called “Steady State”CMOS Dynamic Behavior- Also called “AC“ performanceUniversity of Electronic Science and Technology of China Digital Logic circuit and systemVDD = +5.0VVOUTVINTpTn1、 Static Electrical Behavior1） Logic Levels & Noise MarginsUniversity of Electronic
5、 Science and Technology of China Digital Logic circuit and systemThe output voltage is changed When input voltage changed.The steady state model of CMOSUniversity of Electronic Science and Technology of China Digital Logic circuit and systemIdeal Buffer: Real Buffer:NMH = NML = VDD/2 NMH , NML VDD/2
6、DC Transfer CharacteristicsUniversity of Electronic Science and Technology of China Digital Logic circuit and systemAnything that degrades the signalE.g., resistance, power supply noise, coupling to neighboring wires, etc.Example: a gate (driver) outputs 5 V but, because of resistance in a long wire
7、, receiver gets 4.5 VWhat is Noise?University of Electronic Science and Technology of China Digital Logic circuit and systemVDDVoutHIGHVOHminVSS LOWVOLmaxVDDHIGHVIHminVSSLOWVILmaxVinNoise MarginNoise MarginHIGH State Noise Margin LOW State Noise Margin :How much noise it takes to corrupt a worst-case output voltage into a value that may not be recognized properly by an input.(多大的噪声会使最坏输出电压被破坏得不可识别 )DC Noise Margin（直流噪声容限 ）：VNH=VOHmin - VIHminVNL=|VOLmax - VILmax|
