4线-2线优先编码器设计、仿真与实现1.真值表：输入输出I0I1I2I3Y1Y0100000X10001XX1010XXX1112.逻辑关系Y1 = X0 + X1Y2 = X0 + X1X23.Verolig 代码实现/A 4-2 decordermodule DECODER_4_2(X, Y0, Y1);input 3:0X;output Y0,Y1; wire n0,n1,n2; not (n0,X1);and (n1,n0,X2);assign Y0=(X0|n1); assign Y1=(X0|X1); endmodule4.Quartus II 仿真结果时钟设置：X0 = 10nsx1 = 20nsx2 = 40ns x3 = 80ns输入输出状态表：X0X1X2X3Y0Y10000001000110100011100110010101010110110011110110001001001110101011101110011101011110111011111115.FPGA引脚设置
