FPGA技术课程作业.doc

.1. 分析test2.v程序,完成下列各题：1） 完成程序填空。2） 画出该代码综合后的电路图。module test2 (clk,reset,in1,in2,in3,out1,out2 );input clk,reset;input in1,in2, in3 ;output out1,out2;reg out1,out2; integer temp1,temp2;always (posedge clk or posedge reset) if(reset) begin temp1 = 0; temp2 = 0;end else begin temp1 = in1 & in2;temp2 = in2 | in3;endalways (posedge clk) begin out1 = temp1 & temp2; out2 = temp1 in3; endendmod