状态机：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY xhd ISPort(clk : in std_logic; ra,rb,ya,yb,ga,gb : out std_logic );END xhd;Architecture a of xhd istype state is (S0,S1,S2,S3);signal presentstate,nextstate : state;signal tmp1,tmp2 : integer range 0 to 30;signal timeout1,timeout2: std_logic;signal q: std_logic_vector(21 downto 0);signal sec: std_logic;Begin-get 1 hz clock pulseprocess(clk)beginif clkevent and clk=
