Verilog语言基础知识17页.doc

Verilog HDL语言基础知识 先来看两个Verilog HDL程序。例6.1 一个8位全加器的 Verilog HDL源代码module adder8(cout,sum,ina,inb,cin);output7:0 sum;output cout;input7:0 ina,inb;input cin;assign cout,sum=ina+inb+cin;/全加endmodule【例6.2】一个8位计数器的Verilog HDL源代码module counter8(out,cout,data,load,cin,clk);output7:0 out;output cout;input7:0 data;input load,cin,clk;reg7:0 out;always (posedge clk)beginif(load) out=data;else out=out+cin;endassign cout=&out&ci