verilog编写六-十进制计数器1页.doc

数电实验：用Verilog编写六-十进制计数器十进制计数器：module cnt10(clk,q,cout); input clk; output 3:0q; output cout; reg 3:0q; reg cout; always (posedge clk) begin if(q4b1001) begin q=q+1; cout=0; end else begin q=4b0000; cout=1; end endendmodule六进制计数器：module cnt6(clk,q); input clk; output 3:0q; reg 3:0q; always (posedge clk) begin if(q4b0110) begin