verilog程序-流水灯(共4页).doc

/* 程序功能：流水灯 版本：1.1 版权：分享快乐*/module liu_shui_deng( input wire pin_clk_in, input wire pin_rest_n , input wire 1:0 pin_ctrl, output reg 7:0 pin_led_out );wire clk ; reg 31: 0 counter32;always (posedge pin_clk_in or negedge pin_rest_n) begin if(pin_rest_n=1b0) begin counter32 = 32b0; end else begin