Verilog音乐播放器(共9页).docx

Verilog 音乐播放器1、音符对照表2、顶层结构3、代码3.1、顶层代码：module musicplayer_1 (clk,reset,Q);input clk;input reset;output Q;/-wire clk_MHz;wire clk_4Hz;wire 5:0Index;/64ge yinfuwire 10:0Tone;/2048/-clkMHz u1 (clk,reset,clk_MHz);/bao chi qian hou shun xu yi zhiclk4Hz u2 (clk,reset,clk_4Hz);notetab u3 (clk_4Hz,reset,Index);rom u4 (Index,clk,Tone);singout u5 (clk_MHz,reset,Tone,Q);