基于FPGAverilog数字钟源码(共6页).docx

module Dig_clk(input CLK_50M, input CLK_1HZ,input CLK_1K,input RSTN,input selec,input SET_add,/input SET_sub,output 23:0time_value,output 3:0LED);wire CLK_1S;wire 7:0hour,min,sec;assign LED = mode;wire 3:0mode;set_time D1(.RSTN(RSTN),.TURN(selec),.flag(mode);wire value0,value1,value2;mode_sel D2(.set_add(SET_add),.CLK(CLK_1HZ),.mode(mode2),.value(value2);wire CLK_min,CLK_h;sec_bit D3(.CLK_1S(value2),.RSTN(RSTN