常用时序分析SDC(共59页).docx

常用时序分析SDC命令参考（一）1.Define design environment1.1.Set_operating_conditions1.2.Set_wire_load_model1.3.Set_driving_cell1.4.Set_load1.5.Set_fanout_load1.6.Set_min_library2.Set design constraints2.1.Design rule constraints2.1.1.Set_max_transition2.1.2.Set_max_fanout2.1.3.Set_max_capacitance2.2.Design optimization constraints2.2.1.Create_clock2.2.2.create_generated_clock2.2.3.Set_clock_latency2.2.4.Set_pr