常见面试笔试题-verilog程序库14页.docx

加减法module addsub ( input 7:0 dataa, input 7:0 datab, input add_sub, / if this is 1, add; else subtract input clk, output reg 8:0 result ); always (posedge clk) begin if (add_sub) result = dataa + datab; /or assign cout,sum=dataa+datab; else result = dataa - datab; end endmodule 四位的 全加法器.module add4(cout,sum,a,b,