verilog经典三段式状态机设计实例(共7页).docx

精选优质文档-倾情为你奉上Moore型verilog源代码：FSM实现10010串的检测Moore状态转移图module moorefsm(clk,rst,a,z); input clk,rst; input a; output z; reg z; reg 3:0 currentstate,nextstate; parameter S0 = 4b0000; parameter S1 = 4b0001; parameter S2 = 4b0010; parameter S3 = 4b0011; parameter S4 = 4b0100; parameter S5 = 4b0101; always(posedge clk or negedge rst) begin if(!rst) currentstate = S0;