曼彻斯特编码的verilog实现(共2页).doc

精选优质文档-倾情为你奉上module bianma(din,rst,clk16x,clk96,start,tx,sr,state,clk_en,man);input rst,clk16x,start;input7:0 din;output tx,clk96,sr,state,clk_en,man;reg clk_en;reg7:0 sr;reg clk96;reg tx,man;reg3:0 state;reg2:0 cnt;always (posedge clk16x) begin cnt=cnt+1; if(cnt=7) clk96=clk96; endalways (negedge clk16x or negedge start or posedge rst) begin if(rst) begin clk_en=1d0;end else if(!start) begin clk_en