精选优质文档-倾情为你奉上-VHDL 频率计-一个有效位为4位的十进制的数字频率计。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity freq isport(fsin:in std_logic;-被测信号 clk:in std_logic;-基准时间，1Hz reset : in std_logic; show:out std_logic_vector(6 downto 0);-数码管段码输出 row:out std_logic_vector(3 downto 0);-数码管选择信号end freq;architecture one of freq issignal test_en:std_logic;signal clear:std_logic;-复位信号signal data:std_l
