EDA七段译码器实验报告(共1页).doc

精选优质文档-倾情为你奉上 实验目的掌握七段译码器实验设备quartus II 5.0实验内容library ieee;use ieee.std_logic_1164.all;entity qdymq is port(a:in std_logic_vector(3 downto 0); led:out std_logic_vector(7 downto 0);end qdymq;architecture one of qdymq isbegin with a select led=00111111when0000, 00000110when0001, 01011011when0010, 01001111when0011, 01100110when0100, 01101101when0101, 0111110