内置FIFO的UART设计与实现(共15页).doc

精选优质文档-倾情为你奉上内置FIFO的UART设计与实现一、程序（加批注）library ieee; -U1：RSRuse ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity RSR is port(reset:in std_logic; rx:in std_logic; clk:in std_logic; rx_data:out std_logic_vector(7 downto 0); rx_int:out std_logic);end entity; architecture arc of RSR issignal shifter:std_logic_vector(7 downto 0);signal