1、 LATTICE SEMICONDUCTOR CORPORATION 2003China Distributor FAE TrainingSERDES IntroductionJanuary 2003 Page 1Lattice ConfidentialSERDES Introduction LATTICE SEMICONDUCTOR CORPORATION 2003China Distributor FAE TrainingSERDES IntroductionJanuary 2003 Page 2Lattice ConfidentialAgenda I/O Overview SERDES
2、& CDR Fundamental SERDES Measurements How to Evaluate a SERDES Device? High Speed Design Consideration LATTICE SEMICONDUCTOR CORPORATION 2003China Distributor FAE TrainingSERDES IntroductionJanuary 2003 Page 3Lattice ConfidentialI/O Overview Data transmission, is a means of moving data from one loca
3、tion to another. There are two main parameters that define how the information is transferred. Distance, the space between the sending and the receiving systems speed, the rate at which data has to be passed to the receiving device As Cable length increases, the speed at which the information is tra
4、nsmitted must be lowered in order to keep the bit error rate down LATTICE SEMICONDUCTOR CORPORATION 2003China Distributor FAE TrainingSERDES IntroductionJanuary 2003 Page 4Lattice ConfidentialI/O TypesI/O CELL “Single Ended”I/O Cell “Differential”2 to 5 volt swing100 to 900mV swing LATTICE SEMICONDU
5、CTOR CORPORATION 2003China Distributor FAE TrainingSERDES IntroductionJanuary 2003 Page 5Lattice ConfidentialI/O InterfacesSource-Synchronous,single-endedSource-Synchronous,differentialClock and DataRecovery,differentialInterface“style”Data rate(per pin)1Gbit/s2Gbit/s3Gbit/s4Gbit/sConventional,singl
6、e-endedConventional,differentialPCI, AGP-1XPCI-X, AGP-2XSDR, ZBT, SyncBurstGeneral system logicLVDS CSIXDDR, QDRRapidIOHyperTransportInfiniBandXAUI8b/10b Encoded LVDSn-LVDSUTOPIA-4POS-PHY L4 LATTICE SEMICONDUCTOR CORPORATION 2003China Distributor FAE TrainingSERDES IntroductionJanuary 2003 Page 6Lat
7、tice ConfidentialI/O Timeline Number of Standards Has Increased DramaticallyTTLLVTTL, LVCMOS 3.32002 and beyond1980 19901985 1995PCIAGPLVCMOS 2.5SSTLHSTLCTTGTL+PCI-XLVDSLVPECLLVCMOS 1.8051015Number of standardsI/O Interface Standardson CMOS Devices LATTICE SEMICONDUCTOR CORPORATION 2003China Distrib
8、utor FAE TrainingSERDES IntroductionJanuary 2003 Page 7Lattice ConfidentialAgenda I/O Overview SERDES & CDR Fundamental SERDES Measurements How to Evaluate a SERDES Device? High Speed Design Consideration LATTICE SEMICONDUCTOR CORPORATION 2003China Distributor FAE TrainingSERDES IntroductionJanuary
9、2003 Page 8Lattice ConfidentialParallel vs. Serial Data Transfer Parallel data transfer Multiple lines consume board space Lines interfere with each other Each line needs its own termination circuitry Serial Data Transfer Fewer lines yields reduced board space Line interference can be minimized Uses
10、 a fraction of the termination circuitry vs. parallel No Skew IssuesBackplaneBackplaneA SERDES provides a means to convert a wide parallel data bus to an equivalent bandwidth Single wire serial stream LATTICE SEMICONDUCTOR CORPORATION 2003China Distributor FAE TrainingSERDES IntroductionJanuary 2003
11、 Page 9Lattice ConfidentialWhy SERDES? At Very High Speeds, Board-Level Parallel Data Becomes Nearly Impossible to Manage Variances in Trace Characteristics and Lengths Contribute to Skew: Data to Data Skew Clock to Data Skew Trace count and crosstalk Backplane Cost is proportional to traces and ske
12、w requirements Logic is Best Performed on Parallel Data A SERDES Allows the Best of Both Worlds Serial Data with an Embedded Clock for Distributing Across Backplanes Parallel Data with Separate Clock for Logic ManipulationLogicFromBackplaneToBackplaneSERDESCLK CLK LATTICE SEMICONDUCTOR CORPORATION 2
13、003China Distributor FAE TrainingSERDES IntroductionJanuary 2003 Page 10Lattice ConfidentialSERDES Functionality A SERDES has a: Transmit section (SERializer) and a Receive section (DESerializer), also know as a CDR The transmit portion integrates: DATA with a CLOCK signal to modulate the clock pulse (Similar to Manchester encoding)CLKSERDESData 9:0 100 MHzEmbedded Clock and Serial Data 1 Gbps100 MHz11 Traces Vs 1(actually 1 pair of traces)
