1、VHDL 电子时钟程序最近收到网上朋友们来信咨询如何设计电子时钟，也有很多热心朋友把他设计的时钟或时钟程序发给我。因时间和水平有限不能一一回复和审查到底哪些是合格或是网络转载的。但是感觉可能对部分网友会有所用处，就把自己手头已有的一些时钟设计的相关资料放到网上，希望大家能多多包涵。我会不定时的把一些时钟设计资料上传到本博客，希望多多关注。下面是电子时钟设计的部分 VHDL 程序代码。VHDL 电子钟程序（小时和分钟）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_U
2、NSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity hours isPort ( rst4,selector3,ky_3j : in STD_LOGIC;C10 : in std_logic;dat40 : out std_logic_vector(7 downto 0);end hours;architecture Beha
3、vioral of hours issignal dat41,dat42 : std_logic_vector(7 downto 0):=(others =0);beginprocess(rst4,C10,ky_3j)begincase selector3 iswhen 1 = dat42 dat410);elsif C10event and C10=1 then if dat42(7 downto 4)=“0010“ and dat42(3 downto 0)=“0011“then dat42null; end case;end process; end Behavioral;VHDL 电子
4、钟程序（分频和秒计数）library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity miseconds isPort ( clk_100HZ,rst1 : i
5、n STD_LOGIC;A : out std_logic;dat10 : out std_logic_vector(7 downto 0);end miseconds;architecture Behavioral of miseconds issignal dat1 : std_logic_vector(7 downto 0):=(others =0);beginprocess(clk_100HZ,rst1)begin if(rst1 = 0) then dat10);elsif clk_100HZevent and clk_100HZ=1 then if dat1(7 downto 4)
6、=“1001“ and dat1(3 downto 0)=“1001“then A sin sin sin sin sin sin sin sin null ;end case ;end if ;end process P1;P2 : process(clk_1MHZ)begin if clk_1MHZevent and clk_1MHZ =1 then cnt8 led8s(6 downto 0) led8s(6 downto 0) led8s(6 downto 0) led8s(6 downto 0) led8s(6 downto 0) led8s(6 downto 0) led8s(6
7、downto 0) led8s(6 downto 0) led8s(6 downto 0) led8s(6 downto 0) null ;end case ;end process P3;bt1(0) = sin(0) ;bt1(1) = sin(1) ;bt1(2) = sin(2) and clks(0) ;bt1(3) = sin(3) and clks(1) ;bt1(4) = sin(4) and clks(2) ;bt1(5) = sin(5) and clks(3) ;bt1(6) = sin(6) and clks(4) ;bt1(7) = sin(7) and clks(5) ;bt(0)=not(bt1(0)and T);bt(1)=not(bt1(1)and T);bt(2)=not(bt1(2)and T);bt(3)=not(bt1(3)and T);bt(4)=not(bt1(4)and T);bt(5)=not(bt1(5)and T);bt(6)=not(bt1(6)and T);bt(7)=not(bt1(7)and T);end Behavioral;
